View M36DR432BD85ZA6T_2624764.PDF datasheet online --- IC-ON-LINE

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1/52 february 2003 m36dr432ad m36dr432bd 32 mbit (2mb x16, dual bank, page) flash memory and 4 mbit (256kb x16) sram, multiple memory product features summary n multiple memory product C 1 bank of 32 mbit (2mb x16) flash memory C 1 bank of 4 mbit (256kb x16) sram n supply voltage Cv ddf = v dds =1.65v to 2.2v Cv ppf = 12v for fast program (optional) n access times: 85ns, 100ns, 120ns n low power consumption n electronic signature C manufacturer code: 0020h C top device code, m36dr432ad: 00a0h C bottom device code, m36dr432bd: 00a1h flash memory n memory blocks C dual bank memory array: 4 mbit, 28 mbit C parameter blocks (top or bottom location) n programming time C 10s by word typical C double word program option n asynchronous page mode read C page width: 4 words C page access: 35ns C random access: 85ns, 100ns, 120ns n dual bank operations C read within one bank while program or erase within the other C no delay between read and write operations n block locking C all blocks locked at power up C any combination of blocks can be locked Cwpf for block lock-down n common flash interface (cfi) C 64 bit unique device identifier C 64 bit user programmable otp cells figure 1. package n erase suspend and resume modes n 100,000 program/erase cycles per block n 20 years data retention C defectivity below 1ppm/year sram n 4 mbit (256kb x16) n low v dds data retention: 1.0v n power down features using two chip enable inputs fbga stacked lfbga66 (za) 12 x8mm
m36dr432ad, m36dr432bd 2/52 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a0-a17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a18-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash chip enable (ef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash output enable (gf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write enable (wf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write protect (wpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write protect (wpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash reset/power-down (rpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 vddf supply voltage (1.65v to 2.2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 v ppf programming voltage (11.4v to 12.6v).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ssf ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram chip enable (es). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram write enable (ws). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram output enable (gs).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram upper byte enable (ubs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram lower byte enable (lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 vdds supply voltage (1.65v to 2.2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. main operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. flash bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. flash security block and protection register memory map . . . . . . . . . . . . . . . . . . . . . . 13 flash bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic flash standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dual bank operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash command interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 flash read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 flash read cfi query command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/52 m36dr432ad, m36dr432bd auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 set configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 double word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quadruple word program command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 enter bypass mode command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 exit bypass mode command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program in bypass mode command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 double word program in bypass mode command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 quadruple word program in bypass mode command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bank erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. flash commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. flash read block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. read protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 19 flash block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 reading a blocks lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. flash lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 polling and toggle bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. polling and toggle bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 sram component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
m36dr432ad, m36dr432bd 4/52 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. absolute maximum ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 15. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. flash dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. sram dc characteristics (t a = C40 to 85c; v ddf = v dds = 1.65v to 2.2v) . . . . . . . . 28 figure 8. flash random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. flash page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. flash read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 10. flash write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. flash write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. flash write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 20. flash write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. flash reset/power-down ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21. flash reset/power-down ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. flash data polling dq7 ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. flash data toggle dq6, dq2 ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22. flash data polling and toggle bits ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. flash data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 16. flash data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. sram read mode ac waveforms, address controlled with ubs = lbs = v il . . . . . . 38 figure 18. sram read ac waveforms, es or gs controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 19. sram standby ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. sram read ac characteristics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20. sram write ac waveforms, ws controlled with gs low . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. sram write ac waveforms, ws controlled with gs high . . . . . . . . . . . . . . . . . . . . . . 40 figure 22. sram write cycle waveform, ubs and lbs controlled, g low . . . . . . . . . . . . . . . . . 41 figure 23. sram write ac waveforms, es controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 24. sram low v dds data retention ac waveforms, es controlled . . . . . . . . . . . . . . . . . 42 table 25. sram low v dds data retention characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . 43 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 25. stacked lfbga 12x8mm - 8x8 ball array, 0.8mm pitch, bottom view package outline 44 table 26. stacked lfbga 12x8mm - 8x8 ball array, 0.8mm pitch, package mechanical data . . . 44
5/52 m36dr432ad, m36dr432bd part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 appendix a. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 28. bank a, top boot block addresses m36dr432ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. bank b, top boot block addresses m36dr432ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 30. bank b, bottom boot block addresses m36dr432bd . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 31. bank a, bottom boot block addresses m36dr432bd . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix b. common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 32. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 33. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 34. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 35. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
m36dr432ad, m36dr432bd 6/52 summary description the m36dr432ad/bd is a low-voltage multiple memory product which combines two memory de- vices: a 32 mbit (2mbit x16) non-volatile flash memory and a 4 mbit sram. the memory is available in a stacked lfbga66 12x8mm - 8x8 active ball array, 0.8mm pitch pack- age and supplied with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai07309b 21 a0-a20 wf dq0-dq15 v ddf m36dr432ad m36dr432bd ef v ssf 16 gf rpf wpf v ppf e1s gs ws ubs lbs v sss v dds e2s a0-a17 address inputs a18-a20 address inputs for flash chip only dq0-dq15 data input/outputs, command inputs v ddf flash power supply v ppf flash optional supply voltage for fast program & erase v ssf flash ground v dds sram power supply v sss sram ground nc not connected internally flash control functions ef chip enable gf output enable wf write enable rpf reset/power-down wpf write protect input sram control functions e 1 s chip enable e2s chip enable gs output enable ws write enable ubs upper byte enable lbs lower byte enable
7/52 m36dr432ad, m36dr432bd figure 3. tfbga connections (top view through package) ai90204 a 8 7 6 5 4 3 2 1 e b f a12 a13 a11 a20 nc nc e2s dq12 v sss a2 a3 a6 a7 a18 ef a0 a4 nc nc dq4 ws dq15 a9 a16 dq6 dq13 nc wf a8 a10 a5 nc v ssf a17 rpf a15 a14 nc nc v ddf e1s a1 nc nc gf v dds dq7 dq5 dq14 nc v ssf nc #4 #3 c dq10 dq11 a19 wpf v ppf dq3 dq2 d dq8 dq9 gs lbs ubs dq1 dq0 g h #2 #1
m36dr432ad, m36dr432bd 8/52 signal descriptions see figure 2 logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a17). addresses a0-a17 are common inputs for the flash and the sram components. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they con- trol the commands sent to the command interface of the internal state machine. during a write oper- ation, the address inputs for the flash memory are latched on the falling edge of the flash chip en- able (ef ) or write enable (wf ), whichever occurs last, whereas for the sram array they are latched on the falling edge of the sram chip enable lines (e1s or e2s) or write enable (ws ). in the rest of the datasheet, only the active low sram chip enable line will be discussed. it will be referred to as es . address inputs (a18-a20). addresses a18-a20 are inputs for the flash component only. they are latched during a write operation on the falling edge of flash chip enable (ef ) or write enable (wf ), whichever occurs last. data input/output (dq0-dq15). the data i/o output the data stored at the selected address dur- ing a bus read operation or input a command or the data to be programmed during a write bus op- eration. the input is data to be programmed in the flash or sram memory array or a command to be written to the c.i. of the flash memory. both are latched on the rising edge of flash write enable (wf ) and, sram chip enable lines (es ) or write enable (ws ). the output is data from the flash memory array or sram array, the electronic signature manufacturer or device codes, the block protec- tion status, the configuration register status or the status register data (polling bit dq7, toggle bits dq6 and dq2, error bit dq5 or erase timer bit dq3) depending on the address. outputs are valid when flash chip enable (ef ) and output en- able (gf ) or sram chip enable lines (es ) and output enable (gs ) are active. the output is high impedance when both the flash chip and the sram chip are deselected or the out- puts are disabled and when reset (rpf ) is at v il . flash chip enable (ef ). the chip enable input activates the flash memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v ih the memory is deselected and the power consumption is reduced to the standby level. flash output enable (gf ). gates the outputs through the data buffers during a read operation. when output enable, gf , is at v ih the outputs are high impedance. flash write enable ( wf ). the write enable controls the bus write operation of the flash memorys command interface. flash write protect (wpf ). write protect is an input that gives an additional hardware protection for each flash block. when write protect is at v il , the locked-down blocks cannot be locked or un- locked. when write protect is at v ih , the lock- down is disabled and the locked-down blocks can be locked or unlocked. refer to table 8, read protection register. flash reset/power-down (rpf ). the reset/ power-down input provides hardware reset of the flash memory, and/or power-down functions, de- pending on the flash configuration register sta- tus. reset or power-down of the memory is achieved by pulling rpf to v il for at least t plph . the reset/power-down function is set in the con- figuration register (see set configuration regis- ter command). if it is set to 0 the reset function is enabled, if it is set to 1 the power-down func- tion is enabled. after a reset or power-up the power save function is disabled and all blocks are locked. the memory command interface is reset on pow- er up to read array. either chip enable or write enable must be tied to v ih during power up to al- low maximum security and the possibility to write a command on the first rising edge of write enable. after a reset, when the device is in read, erase suspend read or standby, valid data will be out- put t phq7v1 after the rising edge of rpf . if the de- vice is in erase or program, the operation will be aborted and the reset recovery will take a maxi- mum of t plq7v . the memory will recover from re- set/power-down t phq7v2 after the rising edge of rpf . see tables 18 and 19, and figure 12. v ddf supply voltage (1.65v to 2.2v). v ddf pro- vides the power supply to the internal core and i/o pins of the memory device. it is the main power supply for all operations (read, program and erase). v ppf programming voltage (11.4v to 12.6v). v ppf provides a high voltage power supply for fast factory programming. v ppf is required to use the double word and quadruple word program com- mands. v ssf ground. v ssf ground is the reference for the core supply. it must be connected to the sys- tem ground. sram chip enable (es ). the chip enable in- puts for sram activate the memory control logic, input buffers and decoders. es at v ih deselects
9/52 m36dr432ad, m36dr432bd the memory and reduces the power consumption to the standby level. es can also be used to con- trol writing to the sram memory array, while ws remains at v il . it is not allowed to set ef at v il and es at v il at the same time. sram write enable (ws ). the write enable in- put controls writing to the sram memory array. ws is active low. sram output enable (gs ). the output enable gates the outputs through the data buffers during a read operation of the sram chip. gs is active low. sram upper byte enable (ubs ). enables the upper bytes for sram (dq8-dq15). ubs is active low. sram lower byte enable (lbs ). enables the lower bytes for sram (dq0-dq7). lbs is active low. v dds supply voltage (1.65v to 2.2v). v dds is the sram power supply for all operations. note: each device in a system should have v ddf and v ppf decoupled with a 0.1f capaci- tor close to the pin. see figure 7, ac measure- ment load circuit. the pcb trace widths should be sufficient to carry the required v ppf program and erase currents.
m36dr432ad, m36dr432bd 10/52 functional description the flash and sram components have separate power supplies and grounds and are distinguished by three chip enable inputs: ef for the flash mem- ory and es (e1s and e2s, respectively) for the sram. figure 4. functional block diagram ai07310b flash memory 32 mbit (2mb x 16) v ssf rpf wpf e2s gs ws dq0-dq15 v ddf v ppf a18-a20 a0-a17 sram 4 mbit (256kb x 16) v sss v dds ef gf wf ubs lbs e1s
11/52 m36dr432ad, m36dr432bd table 2. main operation modes note: 1. x = don't care (v il or v ih ). 2. if ubs and lbs are tied together the bus is at 16 bit. for an 8 bit bus configuration use ubs and lbs separately. operation mode ef gf wf rpf wpf es gs ws ubs , lbs (1) dq15-dq0 flash memory read v il v il v ih v ih v ih sram must be disabled data output page read v il v il v ih v ih v ih sram must be disabled data output write v il v ih v il v ih v ih sram must be disabled data input standby v ih xx v ih v ih any sram mode is allowed hi-z reset/ power-down xxx v il v ih any sram mode is allowed hi-z output disable v il v ih v ih v ih v ih any sram mode is allowed hi-z sram read flash must be disabled v il v il v ih v il data out word read write flash must be disabled v il v ih v il v il data in word write standby/power down any flash mode is allowable v ih x x x hi-z xxx v ih hi-z data retention any flash mode is allowable v ih x x x hi-z xxx v ih hi-z output disable any flash mode is allowable v il v ih v ih x hi-z
m36dr432ad, m36dr432bd 12/52 flash memory component the flash memory is a 32 mbit (2mbit x16) non- volatile flash memory that may be erased electri- cally at block level and programmed in-system on a word-by-word basis using a 1.65v to 2.2v v ddf supply for the circuitry and a 1.65v to 2.2v v ddqf supply for the input/output pins (in the stacked de- vice, v ddf and v ddqf are tied internally). an op- tional 12v v ppf power supply is provided to speed up customer programming. the flash device features an asymmetrical block architecture with an array of 71 blocks divided into two banks, banks a and b, providing dual bank operations. while programming or erasing in bank a, read operations are possible in bank b or vice versa. only one bank at a time is allowed to be in program or erase mode. the bank architecture is summarized in table 3, and the block addresses are shown in appendix a. the parameter blocks are located at the top of the memory address space for the m36dr432ad and, at the bottom for the m36dr432bd. each block can be erased separately. erase can be suspended, in order to perform either read or program in any other block, and then resumed. each block can be programmed and erased over 100,000 cycles. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have two levels of protection. they can be individually locked and locked-down preventing any acciden- tal programming or erasure. all blocks are locked at power up and reset. the device includes a 128 bit protection register and a security block to increase the protection of a systems design. the protection register is di- vided into two 64 bit segments. the first segment contains a unique device number written by st, while the second one is one-time-programmable by the user. the user programmable segment can be permanently protected. the security block, pa- rameter block 0, can be permanently protected by the user. figure 5, shows the flash security block and protection register memory map. table 3. flash bank architecture bank size parameter blocks main blocks bank a 4 mbits 8 blocks of 4 kwords 7 blocks of 32 kwords bank b 28 mbits - 56 blocks of 32 kwords
13/52 m36dr432ad, m36dr432bd figure 5. flash security block and protection register memory map flash bus operations the following operations can be performed using the appropriate bus cycles: flash read array (random and page modes), flash write, flash output disable, flash standby and flash reset/ power-down, see table 2, main operation modes. flash read. flash read operations are used to output the contents of the memory array, the elec- tronic signature, the status register, the cfi, the block protection status or the configuration reg- ister status. read operation of the flash memory array is performed in asynchronous page mode, that provides fast access time. data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0-a1 ad- dress inputs. read operations of the electronic signature, the status register, the cfi, the block protection status, the configuration register sta- tus and the security code are performed as single asynchronous read cycles (random read). both flash chip enable ef and flash output enable gf must be at v il in order to read the output of the memory. flash write. write operations are used to give commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable ef and write enable wf are at v il with output enable gf at v ih . addresses are latched on the falling edge of wf or ef whichever occurs last. commands and input data are latched on the rising edge of wf or ef whichever occurs first. noise pulses of less than 5ns typical on ef , wf and gf signals do not start a write cy- cle. flash output disable. the data outputs are high impedance when the output enable gf is at v ih with write enable wf at v ih . flash standby. the memory is in standby when chip enable ef is at v ih and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, inde- pendent of the output enable gf or write enable wf inputs. automatic flash standby. in read mode, after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the cmos standby value, while out- puts still drive the bus. flash power-down. the memory is in power- down when the configuration register is set for/ power-down and rpf is at v il . the power con- sumption is reduced to the power-down level, and outputs are high impedance, independent of the chip enable ef , output enable gf or write en- able wf inputs. dual bank operations. the dual bank allows data to be read from one bank of memory while a program or erase operation is in progress in the other bank of the memory. read and write cycles can be initiated for simultaneous operations in dif- ferent banks without any delay. status register during program or erase must be monitored using an address within the bank being modified. flash command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- ai06185 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 88h 85h 84h 81h 80h security block protection register
m36dr432ad, m36dr432bd 14/52 dles all timings and verifies the correct execution of the program and erase commands. two bus write cycles are required to unlock the command interface. they are followed by a setup or confirm cycle. the increased number of write cycles is to ensure maximum data security. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied or exiting from reset. command sequences must be followed exactly. any invalid combination of commands will reset the device to read mode flash read/reset command. the read/reset command returns the device to read mode. one bus write cycle is required to issue the read/re- set command and return the device to read mode. subsequent read operations will read the ad- dressed location and output the data. the write cy- cle can be preceded by the unlock cycles but it is not mandatory. flash read cfi query command. the read cfi query command is used to read data from the common flash interface (cfi) and the electronic signature (manufacturer or the device code, see table 5). the read cfi query command consists of one bus write cycle. once the command is is- sued the device enters read cfi mode. subse- quent bus read operations read the common flash interface or electronic signature. once the device has entered read cfi mode, only the read/reset command should be used and no oth- er. issuing the read/reset command returns the device to read mode. see appendix b, common flash interface, tables 33, 34, and 35 for details on the information con- tained in the common flash interface memory ar- ea. auto select command. the auto select com- mand uses the two unlock cycles followed by one write cycle to any bank address to setup the com- mand. subsequent reads at any address will out- put the block protection status, protection register and protection register lock or the con- figuration register status depending on the levels of a0 and a1 (see tables 6, 7 and 8). once the auto select command has been issued only the read/reset command should be used and no oth- er. issuing the read/reset command returns the device to read mode. set configuration register command. the flash component contains a configuration regis- ter, see table 7, configuration register. it is used to define the status of the reset/power- down functions. the value for the configuration register is always presented on a0-a15, the other address bits are ignored. address input a10 de- fines the status of the reset/power-down func- tions. if it is set to 0 the reset function is enabled, if it is set to 1 the power-down function is en- abled. at power up the configuration register bit is set to 0. the set configuration register command is used to write a new value to the configuration register. the command uses the two unlock cycles followed by one write cycle to setup the command and a further write cycle to write the data and confirm the command. program command. the program command uses the two unlock cycles followed by a write cy- cle to setup the command and a further write cycle to latch the address and data and start the pro- gram erase controller. read operations within the same bank output the status register after pro- gramming has started. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole bank from 0 to 1. if the program command is used to try to set a bit from 0 to 1 status register error bit dq5 will be set to 1, only if v ppf is in the range of 11.4v to 12.6v. double word program command. this feature is offered to improve the programming throughput by writing a page of two adjacent words in parallel. the v ppf supply voltage is required to be from 11.4v to 12.6v for the double word program com- mand. the command uses the two unlock cycles followed by a write cycle to setup the command. a further two cycles are required to latch the address and data of the two words and start the program erase controller. the addresses must be the same except for the a0. the double word program command can be executed in bypass mode to skip the two unlock cycles. note that the double word program command cannot change a bit set at 0 back to 1. one of the erase commands must be used to set all the bits in a block or in the whole bank from 0 to 1. if the double word program command is used to try to set a bit from 0 to 1 status register error bit dq5 will be set to 1. quadruple word program command. the quadruple word program command improves the programming throughput by writing a page of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. the v ppf supply voltage is required to be from 11.4v to 12.6v for the quadruple word program com- mand.
15/52 m36dr432ad, m36dr432bd the command uses the two unlock cycles followed by a write cycle to setup the command. a further four cycles are required to latch the address and data of the four words and start the program erase controller. the quadruple word program command can be executed in bypass mode to skip the two unlock cycles. note that the quadruple word program command cannot change a bit set to 0 back to 1. one of the erase commands must be used to set all the bits in a block or in the whole bank from 0 to 1. if the quadruple word program command is used to try to set a bit from 0 to 1 status register error bit dq5 will be set to 1. enter bypass mode command. the bypass mode is used to reduce the overall programming time when large memory arrays need to be pro- grammed. the enter bypass mode command uses the two unlock cycles followed by one write cycle to set up the command. once in bypass mode, it is impera- tive that only the following commands be issued: exit bypass, program, double word program or quadruple word program. exit bypass mode command. the exit bypass mode command uses two write cycles to setup and confirm the command. the unlock cycles are not required. after the exit bypass mode com- mand, the device resets to read mode. program in bypass mode command. the program in bypass mode command can be is- sued when the device is in bypass mode (issue a enter bypass mode command). it uses the same sequence of cycles as the program command with the exception of the unlock cycles. double word program in bypass mode com- mand. the double word program in bypass mode command can be issued when the device is in bypass mode (issue a enter bypass mode com- mand). it uses the same sequence of cycles as the double word program command with the excep- tion of the unlock cycles. quadruple word program in bypass mode command. the quadruple word program in by- pass mode command can be iss ued when the de- vice is in bypass mode (issue a enter bypass mode command). it uses the same sequence of cycles as the quadruple word program command with the exception of the unlock cycles. block lock command. the block lock com- mand is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. three bus write cycles are required to issue the block lock command. n the first two bus cycles unlock the command interface. n the third bus cycle sets up the block lock command and latches the block address. the lock status can be monitored for each block using the auto select command. table 10 shows the lock status after issuing a block lock com- mand. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a blocks unlock command. refer to the section, block locking, for a detailed explanation. block unlock command. the blocks unlock command is used to unlock a block, allowing the block to be programmed or erased. three bus write cycles are required to issue the blocks unlock command. n the first two bus cycles unlock the command interface. n the third bus cycle sets up the block unlock command and latches the block address. the lock status can be monitored for each block using the auto select command. table 10 shows the lock status after issuing a block unlock com- mand. refer to the section, block locking, for a detailed explanation. block lock-down command. a locked or un- locked block can be locked-down by issuing the block lock-down command. a locked-down block cannot be programmed or erased, or have its pro- tection status changed when wpf is low, v il . when wpf is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. three bus write cycles are required to issue the block lock-down command. n the first two bus cycles unlock the command interface. n the third bus cycle sets up the block lock- down command and latches the block address. the lock status can be monitored for each block using the auto select command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta- ble 10 shows the lock status after issuing a block lock-down command. refer to the section, block locking, for a detailed explanation. block erase command. the block erase com- mand can be used to erase a block. it sets all the bits within the selected block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the device will return to read array mode. it is not necessary to pre-pro-
m36dr432ad, m36dr432bd 16/52 gram the block as the program/erase controller does it automatically before erasing. six bus write cycles are required to issue the command. n the first two write cycles unlock the command interface. n the third write cycles sets up the command n the fourth and fifth write cycles repeat the unlock sequence n the sixth write cycle latches the block address and confirms the command. additional block erase confirm cycles can be is- sued to erase other blocks without further unlock cycles. all blocks must belong to the same bank; if a new block belonging to the other bank is given, the operation is aborted. the additional block erase confirm cycles must be given within the dq3 erase timeout period. each time a new confirm cycle is issued the timeout pe- riod restarts. the status of the internal timer can be monitored through the level of dq3, see status register section for more details. once the command is issued the device outputs the status register data when any address within the bank is read. after the command has been issued the flash read/reset command will be accepted during the dq3 timeout period, after that only the erase sus- pend command will be accepted. on successful completion of the block erase com- mand, the device returns to read array mode. bank erase command. the bank erase com- mand can be used to erase a bank. it sets all the bits within the selected bank to 1. all previous data in the bank is lost. the bank erase command will ignore any protected blo cks within the bank. if all blocks in the bank are protected then the bank erase operation will abort and the data in the bank will not be changed. it is not necessary to pre-pro- gram the bank as the program/erase controller does it automatically before erasing. as for the block erase command six bus write cy- cles are required to issue the command. n the first two write cycles unlock the command interface. n the third write cycles sets up the command n the fourth and fifth write cycles repeat the unlock sequence n the sixth write cycle latches the block address and confirms the command. once the command is issued the device outputs the status register data when any address within the bank is read. on successful completion of the bank erase com- mand, the device returns to read array mode. erase suspend command. the erase suspend command is used to pause a block erase opera- tion. in a dual bank memory it can be used to read data within the bank where an erase operation is in progress. it is also possible to program data in blocks not being erased. one bus write cycle is required to issue the erase suspend command. the program/erase control- ler suspends the erase operation within 20s of the erase suspend command being issued and bits 7, 6 and/ or 2 of the status register are set to 1. the device is then automatically set to read mode. the command can be addressed to any bank. during erase suspend the memory will accept the erase resume, program, read cfi query, auto select, block lock, block unlock and block lock- down commands. erase resume command. the erase resume command can be used to restart the program/ erase controller after an erase suspend com- mand has paused it. one bus write cycle is re- quired to issue the command. the command must be issued to an address within the bank being erased. the unlock cycles are not required. protection register program command. the protection register program command is used to program the protection register (one-time-pro- grammable (otp) segment and protection regis- ter lock). the otp segment is programmed 16 bits at a time. when shipped all bits in the segment are set to 1. the user can only program the bits to 0. four write cycles are required to issue the protec- tion register program command. n the first two bus cycles unlock the command interface. n the third bus cycle sets up the protection register program command. n the fourth latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the otp segment can be protected by program- ming bit 1 of the protection register lock. the segment can be protected by programming bit 1 of the protection register lock. bit 1 of the protec- tion register lock also protects bit 2 of the protec- tion register lock. programming bit 2 of the protection register lock will result in a permanent protection of parameter block #0 (see figure 5, flash security block and protection register memory map). attempting to program a previously
17/52 m36dr432ad, m36dr432bd protected protection register will result in a status register error. the protection of the protection register and/or the security block is not revers- ible. table 4. flash commands note: x = don't care, ba = block address, pa = program address, pd = program data, crd = configuration register data. for coded cycles address inputs a12-a20 are don't care. commands no of cycles bus operations 1st 2nd 3rd 4th 5th 6th 7th add data add data add data add data add data add data add data read/reset 1+ x f0h read memory array until a new write cycle is initiated. 3+ 555h aah 2aah 55h 555h f0h read memory array until a new write cycle is initiated. cfi query 1+ 55h 98h read cfi and electronic signature until a read/reset command is issued. auto select 3+ 555h aah 2aah 55h 555h 90h read protection register, block protection or configuration register status until a read/reset command is issued. set configuration register 4 555h aah 2aah 55h 555h 60h crd 03h program 4 555h aah 2aah 55h 555h a0h pa pd read data polling or toggle bit until program completes. double word program 5 555h aah 2aah 55h 555h 40h pa1 pd1 pa2 pd2 quadruple word program 5 555h aah 2aah 55h 555h 50h pa1 pd1 pa2 pd2 pa3 pd3 pa4 pd4 enter bypass mode 3 555h aah 2aah 55h 555h 20h exit bypass mode 2 x 90h x 00h program in bypass mode 2 x a0h pa pd read data polling or toggle bit until program completes. double word program in bypass mode 3 x 40h pa1 pd1 pa2 pd2 quadruple word program in bypass mode 3 x 50h pa1 pd1 pa2 pd2 pa3 pd3 pa4 pd4 block lock 4 555h aah 2aah 55h 555h 60h ba 01h block unlock 4 555h aah 2aah 55h 555h 60h ba d0h block lock-down 4 555h aah 2aah 55h 555h 60h ba 2fh block erase 6+ 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba 30h bank erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba 10h erase suspend 1 x b0h read until toggle stops, then read all the data needed from any blocks not being erased then resume erase. erase resume 1 ba 30h read data polling or toggle bits until erase completes or erase is suspended another time protection register program 4 555h aah 2aah 55h pa c0h pa pd
m36dr432ad, m36dr432bd 18/52 table 5. read electronic signature note: x = don't care. table 6. flash read block protection note: x = don't care. table 7. configuration register note: x = don't care. code device ef gf wf a0 a1 a7-a2 a8-a20 dq15-dq0 manufacturer code v il v il v ih v il v il 0 x 0020h device code m36dr432ad v il v il v ih v ih v il 0 x 00a0h m36dr432bd v il v il v ih v ih v il 0 x 00a1h block status ef gf wf a0 a1 a20-a12 a7-a2 other addresses dq0 dq1 dq15-dq2 locked block v il v il v ih v il v ih block address 0 x 1 0 0000h unlocked block v il v il v ih v il v ih block address 0 x 0 0 0000h locked-down block v il v il v ih v il v ih block address 0 x x 1 0000h rpf function ef gf wf a0 a1 a7-a2 other addresses dq10 dq9-dq0 dq15-dq11 reset v il v il v ih v ih v ih 0 x 0 don't care reset/power-down v il v il v ih v ih v ih 0 x 1 don't care
19/52 m36dr432ad, m36dr432bd table 8. read protection register note: x= don't care. table 9. program, erase times and program, erase endurance cycles note: 1. excludes the time needed to execute the sequence for program command. 2. same timing value if v ppf = 12v flash block locking the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has two levels of protection. n lock/unlock - this first level allows software- only control of block locking. n lock-down - this second level requires hardware interaction before locking can be changed. the protection status of each block can be set to locked, unlocked, and lock-down. table 10, de- fines all of the possible protection states (wpf , dq1, dq0). reading a blocks lock status the lock status of every block can be read in the auto select mode of the device. subsequent reads at the address specified in table 6, will out- put the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indi- cates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- word e f g f w f a20-a8 a7-0 dq15-8 dq7-3 dq2 dq1 dq0 lock v il v il v ih x 80h xxh 00000b security prot.data otp prot.data 0 unique id 0 v il v il v ih x 81h id data id data id data id data id data unique id 1 v il v il v ih x 82h id data id data id data id data id data unique id 2 v il v il v ih x 83h id data id data id data id data id data unique id 3 v il v il v ih x 84h id data id data id data id data id data otp 0 v il v il v ih x 85h otp data otp data otp data otp data otp data otp 1 v il v il v ih x 86h otp data otp data otp data otp data otp data otp 2 v il v il v ih x 87h otp data otp data otp data otp data otp data otp 3 v il v il v ih x 88h otp data otp data otp data otp data otp data parameter m36dr432ad, m36dr432bd unit min max typ typical after 100k w/e cycles parameter block (4 kword) erase (preprogrammed) 2.5 0.3 1 s main block (32 kword) erase (preprogrammed) 4 0.8 3 s bank erase (preprogrammed, bank a) 3 6 s bank erase (preprogrammed, bank b) 20 30 s chip program (1) 20 25 s chip program (double word, v ppf = 12v) (1) 8s word program (2) 100 10 s double word program (v ppf = 12v) 100 8 s quadruple word program (v ppf = 12v) 100 8 s program/erase cycles (per block) 100,000 cycles
m36dr432ad, m36dr432bd 20/52 ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will reset the device to read array mode. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wpf input pin. when wpf =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wpf =1 (v ih ) the lock-down function is disabled (1,1,1) and locked-down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wpf remains high. when wpf is low, blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wpf was high. device reset or power-down resets all blocks, including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete.
21/52 m36dr432ad, m36dr432bd table 10. flash lock status note: 1. the lock status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a locked block) a s read in the auto select command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wpf status. 3. a wpf transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. flash status register the status register provides information on the current or previous program or erase operations. bus read operations from any address within the bank, always read the status register during pro- gram and erase operations. the various bits convey information about the sta- tus and any errors of the operation. the bits in the status register are summarized in table 12, status register bits. refer to tables 11 and 12 in conjunction with the following text de- scriptions. data polling bit (dq7). when program opera- tions are in progress, the data polling bit outputs the complement of the bit being programmed on dq7. for a double word program operation, it is the complement of dq7 for the last word written to the command interface. during an erase operation, it outputs a '0'. after completion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/ e.c. operation, that is after the fourth wf pulse for programming or after the sixth wf pulse for erase. it must be performed at the address being pro- grammed or at an address within the block being erased. see figure 22 for the data polling flow- chart and figure 13 for the data polling wave- forms. dq7 will also flag an erase suspend by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an address within a block being erased must be provided. dq7 will output '1' if the read is attempt- ed on a block being erased and the data value on other blocks. during a program operation in erase suspend, dq7 will have the same behavior as in the normal program. toggle bit (dq6). when program or erase oper- ations are in progress, successive attempts to read dq6 will output complementary data. dq6 will toggle following the toggling of either gf or ef . the operation is completed when two successive reads give the same output data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. op- erations, that is after the fourth wf pulse for pro- gramming or after the sixth wf pulse for erase. dq6 will be set to '1' if a read operation is attempt- ed on an erase suspend block. when erase is suspended dq6 will toggle during programming operations in a block different from the block in erase suspend. see figure 16 for toggle bit flowchart and figure 14 for toggle bit waveforms. toggle bit (dq2). toggle bit dq2, together with dq6, can be used to determine the device status during erase operations. during erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will output data. dq2 will be set to '1' during program operation and to 0 in erase operation. if a read operation is addressed to a block where an erase error has occurred, dq2 will toggle. current protection status (1) (wpf , dq1, dq0) next protection status (1) (wpf , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wpf transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
m36dr432ad, m36dr432bd 22/52 error bit (dq5). the error bit can be used to identify if an error occurs during a program or erase operation. the error bit is set to 1 when a program or erase operation has failed. when it is set to 0 the pro- gram or erase operation was successful. if any program command is used to try to set a bit from 0 to 1 status register error bit dq5 will be set to 1, only if v pp is in the range of 11.4v to 12.6v. the error bit is reset by a read/reset command. erase timer bit (dq3). the erase timer bit is used to indicate the timeout period for an erase operation. when the last block erase command has been en- tered to the command interface and it is waiting for the erase operation to start, the erase timer bit is set to 0. when the erase timeout period is fin- ished, dq3 returns to 1, (80s to 120s). dq0, dq1 and dq4 are reserved for future use and should be masked. table 11. polling and toggle bits mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle n/a erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle 1
23/52 m36dr432ad, m36dr432bd table 12. status register bits note: 1. logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. 2. in case of double word program dq7 refers to the last word input. dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend. indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase in progress dq program complete or data of non erase block during erase suspend. dq program in progress (2) 6 toggle bit '-1-0-1-0-1-0-1-' erase or program in progress successive reads output complementary data on dq6 while programming or erase operations are in progress. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase in progress 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend '0' erase timeout period in progress an additional block to be erased in parallel can be entered to the p/e.c provided that it belongs to the same bank 2 toggle bit '-1-0-1-0-1-0-1-' erase suspend read in the erase suspended block. erase error due to the currently addressed block (when dq5 = '1'). indicates the erase status and allows to identify the erased block. 1 program in progress or erase complete. dq erase suspend read on non erase suspend block. 1 reserved 0 reserved
m36dr432ad, m36dr432bd 24/52 sram component the sram is a 4 mbit (256kb x16) low-power con- sumption memory array with low v dds data reten- tion. sram operations the following operations can be performed using the appropriate bus cycles: read array, write ar- ray, output disable, power down (see table 2). read. read operations are used to output the contents of the sram array. the sram is in read mode whenever write enable (ws ) is at v ih with output enable (gs ) at v il , chip enable es and ubs , lbs combinations are asserted. valid data will be available at the output pins within t avqv after the last stable address, provided that gs is low and es is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv or t glqv ) rather than the address. data out may be indeterminate at t elqx and t glqx , but data lines will always be valid at t avqv (see table 23, figures 17 and 18). write. write operations are used to write data in the sram. the sram is in write mode whenever the ws and es pins are at v il . either the chip en- able input (es ) or the write enable input (ws ) must be de-asserted during address transitions for subsequent write cycles. write begins with the concurrence of chip enable being active and ws at v il . a write begins at the latest transition among es going to v il and ws going to v il . therefore, address setup time is referenced to write enable and chip enable as t avwl and t avel respectively, and is determined by the latter occur- ring edge. the write cycle can be terminated by the rising edge of es or the rising edge of ws , whichever occurs first. if the output is enabled (es =v il and gs =v il ), then ws will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the ris- ing edge of write enable, or for t dveh before the rising edge of es , whichever occurs first, and re- main valid for t whdx and t ehax (see table 24, fig- ure 20, 22, 24). standby/power-down. the sram chip has a chip enable power-down feature which invokes an automatic standby mode (see table 23, figure 19) whenever either chip enable is de-asserted (es =v ih ). data retention. the sram data retention per- formances as v dds go down to v dr are described in table 25 and figure 24. in es controlled data retention mode, minimum standby current mode is entered when es 3 v dds C0.2v. output disable. the data outputs are high im- pedance when the output enable (gs ) is at v ih with write enable (ws ) at v ih .
25/52 m36dr432ad, m36dr432bd maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 13. absolute maximum ratings (1) note: 1. m inimum voltage may undershoot to C2v during transition and for less than 20ns. 2. depends on range. 3. v dd = v dds = v ddf . symbol parameter value unit t a ambient operating temperature (3) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 150 c v io (2) input or output voltage C0.5 to v dd (3) +0.5 v v ddf supply voltage C0.5 to 2.7 v v dds sram chip supply voltage C0.5 to 2.4 v v ppf program voltage C0.5 to 13 v
m36dr432ad, m36dr432bd 26/52 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 14, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 14. operating and ac measurement conditions note: 1. v dd = v dds = v ddf figure 6. ac measurement i/o waveform note: v dd means v ddf = v dds figure 7. ac measurement load circuit note: v dd means v ddf = v dds table 15. device capacitance note: sampled only, not 100% tested. sram flash parameter 70 85 100, 120 units min max min max min max v ddf supply voltage - - 1.8 2.2 1.65 2.2 v v dds supply voltage 1.65 2.2 ----v v ppf supply voltage 11.4 12.6 11.4 12.6 v ambient operating temperature C 40 85 C 40 85 C 40 85 c load capacitance (c l ) 30 5 30 30 pf input rise and fall times 2 4 4 ns input pulse voltages (1) 0 to v dd 0 to v dd 0 to v dd v input and output timing ref. voltages (1) v dd /2 v dd /2 v dd /2 v ai90206 v dd 0v v dd /2 ai90207 c l = 50pf c l includes jig capacitance device under test 25k w v dd 25k w vdd 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf
27/52 m36dr432ad, m36dr432bd table 16. flash dc characteristics note: 1. sampled only, not 100% tested. 2. v ppf may be connected to 12v power supply for a total of less than 100 hrs. 3. for standard program/erase operation v ppf is dont care. symbol parameter test condition min typ max unit i li input leakage current 0v v in v dd 1 a i lo output leakage current 0v v out v dd 5 a i cc1 supply current (read mode) e f = v il , g f = v ih , f = 6mhz 36ma i cc2 supply current (power-down) rp f = v ss 0.2v 210a i cc3 supply current (standby) e f = v dd 0.2v 10 50 a i cc4 (1) supply current (program or erase) word program, block erase in progress 10 20 ma i cc5 (1) supply current (dual bank) program/erase in progress in one bank, read in the other bank 13 26 ma i ppf1 v ppf supply current (program or erase) v ppf = 12v 0.6v 25ma i ppf2 v ppf supply current (standby or read) v ppf v dd 0.2 5 a v ppf = 12v 0.6v 100 400 a v il input low voltage C0.5 0.4 v v ih input high voltage v dd C 0.4 v dd + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = C100a v dd C0.1 v v ppf (2,3) v ppf supply voltage (program or erase) C0.4 v dd + 0.4 v double word program 11.4 12.6 v
m36dr432ad, m36dr432bd 28/52 table 17. sram dc characteristics (t a = C40 to 85c; v ddf = v dds = 1.65v to 2.2v) note: 1. i ddes and i ddws are specified with device deselected. if device is read while in erase suspend, current draw is sum of i ddes and i ddr. if the device is read while in program suspend, current draw is the sum of i ddws and i ddr . 2. v in = v il or v ih symbol parameter test condition min typ max unit i oz output leakage current 0v v out v dds, output disabled -1 +1 +1 a i ix input load current 0v v in v dds -1 1 +1 a i dds v dd standby current e s 3 v dds C 0.2v, v in 3 v dds C 0.2v or v in 0.2v, f=0 v dds = 2.2v 110a i dd supply current i out = 0 ma, f = f max = 1/t rc , cmos levels v dds = 2.2v 47ma i out = 0 ma, f = 0hz cmos levels 15ma v il input low voltage v dds = 1.65v C0.5 0.4 v v ih input high voltage v dds = 2.2v 1.4 v dds +0.2v v v ol output low voltage v dds = 1.65v i ol = 0.1a 0.2 v v oh output high voltage v dds = 1.65v i oh = C0.1a 1.4 v
29/52 m36dr432ad, m36dr432bd figure 8. flash random read ac waveforms ai07312 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a20 ef gf dq0-dq15 telqv valid tehqz tghqz note: write enable (w f ) = high.
m36dr432ad, m36dr432bd 30/52 figure 9. flash page read ac waveforms ai07313 ef gf dq0-dq15 a2-a20 valid a0-a1 valid valid tehqx tghqz tghqx tehqz telqv tglqv tavqv valid valid valid valid valid valid tavqv1
31/52 m36dr432ad, m36dr432bd table 18. flash read ac characteristics note: 1. sampled only, not 100% tested. 2. gf may be delayed by up to t elqv - t glqv after the falling edge of ef without increasing t elqv . 3. to be characterized. symbol alt parameter test condition m36dr432ad, m36dr432bd unit 85 100 120 min max min max min max t avav t rc address valid to next address valid ef = v il , gf = v il 85 (3) 100 120 ns t av qv t acc address valid to output valid (random) ef = v il , gf = v il 85 (3) 100 120 ns t av qv 1 t pa ge address valid to output valid (page) ef = v il , gf = v il 30 (3) 35 45 ns t elqx (1) t lz chip enable low to output transition gf = v il 00 0 ns t elqv (2) t ce chip enable low to output valid gf = v il 85 (3) 100 120 ns t glqx (1) t olz output enable low to output transition ef = v il 00 0 ns t glqv (2) t oe output enable low to output valid ef = v il 25 (3) 25 35 ns t ehqx t oh chip enable high to output transition gf = v il 00 0 ns t ehqz (1) t hz chip enable high to output hi-z gf = v il 20 (3) 25 35 ns t ghqx t oh output enable high to output transition ef = v il 00 0 ns t ghqz (1) t df output enable high to output hi-z ef = v il 20 (3) 25 35 ns t axqx t oh address transition to output transition ef = v il , gf = v il 00 0 ns
m36dr432ad, m36dr432bd 32/52 figure 10. flash write ac waveforms, write enable controlled note: addresses are latched on the falling edge of wf , data is latched on the rising edge of wf. table 19. flash write ac characteristics, write enable controlled note: 1. to be characterized. symbol alt parameter m36dr432ad, m36dr432bd unit 85 100 120 min max min max min max t avav t wc address valid to next address valid 85 (1) 100 120 ns t elwl t cs chip enable low to write enable low 0 0 0 ns t wlwh t wp write enable low to write enable high 50 (1) 50 50 ns t dvwh t ds input valid to write enable high 40 (1) 50 50 ns t whdx t dh write enable high to input transition 0 0 0 ns t wheh t ch write enable high to chip enable high 0 0 0 ns t whwl t wph write enable high to write enable low 30 30 30 ns t avw l t as address valid to write enable low 0 0 0 ns t wlax t ah write enable low to address transition 50 50 50 ns t ghwl output enable high to write enable low 0 0 0 ns t vdhel t vcs v dd high to chip enable low 50 50 50 s t whgl t oeh write enable high to output enable low 30 30 30 ns t plq7v rp f low to reset complete during program/erase 15 15 15 s ai07314 ef gf wf a0-a20 dq0-dq15 valid valid v ddf tvdhel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
33/52 m36dr432ad, m36dr432bd figure 11. flash write ac waveforms, chip enable controlled note: addresses are latched on the falling edge of ef , data is latched on the rising edge of ef . table 20. flash write ac characteristics, chip enable controlled note: 1. to be characterized symbol alt parameter m36dr432ad, m36dr432bd unit 85 100 120 min max min max min max t avav t wc address valid to next address valid 85 (1) 100 120 ns t wlel t ws write enable low to chip enable low 0 0 0 ns t eleh t cp chip enable low to chip enable high 50 (1) 50 50 ns t dveh t ds input valid to chip enable high 40 (1) 50 50 ns t ehdx t dh chip enable high to input transition 0 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 30 ns t avel t as address valid to chip enable low 0 0 0 ns t elax t ah chip enable low to address transition 50 50 50 ns t ghel output enable high chip enable low 0 0 0 ns t vdhwl t vcs v dd high to write enable low 50 50 50 s t ehgl t oeh chip enable high to output enable low 30 30 30 ns t plq7v rp f low to reset complete during program/erase 15 15 15 s ai07315 ef gf wf a0-a20 dq0-dq15 valid valid v ddf tvdhwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m36dr432ad, m36dr432bd 34/52 figure 12. flash reset/power-down ac waveform table 21. flash reset/power-down ac characteristics symbol alt parameter test condition m36dr432ad, m36dr432bd unit 85 100 120 min max min max min max t phq7v1 rpf high to data valid (read mode) 150 150 150 ns t phq7v2 rpf high to data valid (reset/power-down enabled) 50 50 50 s t plq7v rpf low to reset complete during program 10 10 10 s during erase 20 20 20 s t plph t rp rpf pulse width 50 50 50 ns ai07316 dq7 wf rpf tplph tphq7v valid read dq7 valid tplq7v program / erase
35/52 m36dr432ad, m36dr432bd figure 13. flash data polling dq7 ac waveforms ai07317 ef gf wf a0-a20 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv
m36dr432ad, m36dr432bd 36/52 figure 14. flash data toggle dq6, dq2 ac waveforms ai06196 ef gf wf a0-a20 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5, dq7-dq15 note: all other timings are as a normal read cycle.
37/52 m36dr432ad, m36dr432bd table 22. flash data polling and toggle bits ac characteristics note: all other timings are defined in read ac characteristics figure 15. flash data polling flowchart figure 16. flash data toggle flowchart symbol parameter m36dr432ad, m36dr432bd unit min max t whq7v write enable high to dq7 valid (program, wf controlled) 8 100 s write enable high to dq7 valid (block erase, wf controlled) 0.8 4 s t ehq7v chip enable high to dq7 valid (program, ef controlled) 8 100 s chip enable high to dq7 valid (block erase, ef controlled) 0.8 4 s t q7vqv q7 valid to output valid (data polling) 0 ns t whqv write enable high to output valid (program) 8 100 s write enable high to output valid (block erase) 0.8 4 s t ehqv chip enable high to output valid (program) 8 100 s chip enable high to output valid (block erase) 0.8 4 s read dq5 & dq7 at valid address start read dq7 fail pass ai06197 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq5 & dq6 start read dq6 fail pass ai06198 dq6 = toggles no no yes yes dq5 = 1 no yes dq6 = toggles
m36dr432ad, m36dr432bd 38/52 figure 17. sram read mode ac waveforms, address controlled with ubs = lbs = v il note: es = low, gs = low, ws = high. figure 18. sram read ac waveforms, es or gs controlled note: write enable (ws ) = high. ai90217 tavav tavqv taxqx a0-a17 dq0-dq15 valid data valid data valid ai07311 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data valid a0-a17 es gs dq0-dq15 valid tblqv tblqx tbhqz ubs, lbs
39/52 m36dr432ad, m36dr432bd figure 19. sram standby ac waveforms table 23. sram read ac characteristics ) note: 1. sampled only. not 100% tested. symbol alt parameter sram unit 70 min max t avav t rc read cycle time 70 ns t avqv t aa address valid to output valid 70 ns t axqx t oh address transition to output transition 10 ns t bhqz t bhz ubs , lbs disable to hi-z output 25 ns t blqv t ba ubs , lbs access time 45 ns t blqx t blz ubs , lbs enable to low-z output 5 ns t ehqz t hz chip enable high to output hi-z 25 ns t elqv t ace chip enable low to output valid 70 ns t elqx t lz chip enable low to output transition 5 ns t ghqz t ohz output enable high to output hi-z 25 ns t glqv t eo output enable low to output valid 35 ns t glqx t olz output enable low to output transition 5 ns t pd (1) chip enable high to power down 70 ns t pu (1) chip enable low to power up 0 ns ai07320 tpd i dd tpu es
m36dr432ad, m36dr432bd 40/52 figure 20. sram write ac waveforms, ws controlled with gs low note: output enable (gs ) = low. figure 21. sram write ac waveforms, ws controlled with gs high ai07321 tavav twhax tdvwh input valid a0-a17 es ws dq0-dq15 valid tavwh twlwh tavwl twlqz twhdx twhqx tblwh ubs, lbs tavel telwh ai07322 tavav twhax tdvwh input valid a0-a17 es ws dq0-dq15 valid tavwh twlwh tavwl twhdx tblwh ubs, lbs tavel telwh gs
41/52 m36dr432ad, m36dr432bd figure 22. sram write cycle waveform, ubs and lbs controlled, g low figure 23. sram write ac waveforms, es controlled note: output enable (gs ) = high. ai07323 tavav tehax a0-a17 es ws dq0-dq15 valid tavwh tblwh ubs, lbs twleh tdvwh input valid twhdx twhqx tavwl twlqz ai07324 tavav tehax tdvwh a0-a17 es ws dq0-dq15 valid tavel twhdx input valid tblwh ubs, lbs telwh twlwh
m36dr432ad, m36dr432bd 42/52 table 24. sram write ac characteristics note: 1. t as is measured from the address valid to the beginning of write. 2. t wr is measured from the end or write to the address change. t wr applied in case a write ends as es or ws goes high. 3. t cw is measured from es going low end of write. 4. a write occurs during the overlap (t wp ) of low es and low ws . a write begins when es goes low and ws goes low with asserting ubs or lbs for single byte operation or simultaneously asserting ubs and lbs for double byte operation. a write ends at the ear- liest transition when es goes high and ws goes high. the t wp is measured from the beginning of write to the end of write. figure 24. sram low v dds data retention ac waveforms, es controlled symbol alt parameter sram unit 70 min max t avav t wc write cycle time 70 ns t av el t as (1) address valid to chip enable low 0 ns t avwh t aw address valid to write enable high 60 ns t av wl t as (1) address valid to write enable low 0 ns t blwh t bw ubs , lbs valid to end of write 60 ns t dv wh t dw input valid to write enable high 30 ns t ehax t wr (2) chip enable high to address transition 0 ns t elwh , t cw (3) chip select to end of write 60 ns t whax t wr (2) write enable high to address transition 0 ns t whdx t dh write enable high to input transition 0 ns t whqx t ow write enable high to output transition 10 ns t wlqz t whz write enable low to output hi-z 25 ns t wlwh t wp (4) write enable pulse width 50 ns ai07325 1.65 v es tcdr es 3 v dds C 0.2v 1.0 v v dr 3 v dds tr data retention mode
43/52 m36dr432ad, m36dr432bd table 25. sram low v dds data retention characteristics (1, 2) note: 1. all other inputs v ih v dds C 0.2v or v il 0.2v. 2. sampled only. not 100% tested. symbol parameter test condition min typical max unit i dddr supply current (data retention) v dds = 1.0v, es 3 v dds C 0.2v no input may exceed v dds + 2v 0.5 10 a v dr supply voltage (data retention) es 3 v dds C 0.2v 1 2.2 v t cdr chip disable to data retention time es 3 v dds C 0.2v 0ns t r operation recovery time t rc ns
m36dr432ad, m36dr432bd 44/52 package mechanical figure 25. stacked lfbga 12x8mm - 8x8 ball array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 26. stacked lfbga 12x8mm - 8x8 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.250 0.0098 a2 1.100 0.0433 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 12.000 C C 0.4724 C C d1 5.600 C C 0.2205 C C d2 8.800 C C 0.3465 C C ddd 0.100 0.0039 e 8.000 C C 0.3150 C C e1 5.600 C C 0.2205 C C e 0.800 C C 0.0315 C C fd 1.600 C C 0.0630 C C fe 1.200 C C 0.0472 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z12 ddd d e e b se fd fe e1 e d1 sd d2 ball "a1"
45/52 m36dr432ad, m36dr432bd part numbering table 27. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available op- tions (speed, package, etc.) or for further information on any aspect of this device, please contact the st- microelectronics sales office nearest to you. example: m36 d r 4 32a d 10 za 6 t device type m36 = mmp (flash + sram) architecture d = dual bank, page mode operating voltage r = v ddf = v dds = 1.65v to 2.2v sram chip size & organization 4 = 4 mbit (256kb x 16 bit) flash specification details 32a = 32 mbit (x16), dual bank: 1/8-7/8 partitioning, top configuration 32b = 32 mbit (x16), dual bank: 1/8-7/8 partitioning, bottom configuration sram specification details d = asynchronous sram, 0. 16m, 70ns speed speed 85 = 85ns (to be characterized) 10 = 100ns 12 = 120ns package za = lfbga66: 0.8mm pitch temperature range 6 = C40 to 85c option t = tape & reel packing
m36dr432ad, m36dr432bd 46/52 appendix a. block addresses table 28. bank a, top boot block addresses m36dr432ad table 29. bank b, top boot block addresses m36dr432ad # size (kword) address range 14 4 1ff000h-1fffffh 13 4 1fe000h-1fefffh 12 4 1fd000h-1fdfffh 11 4 1fc000h-1fcfffh 10 4 1fb000h-1fbfffh 9 4 1fa000h-1fafffh 8 4 1f9000h-1f9fffh 7 4 1f8000h-1f8fffh 6 32 1f0000h-1f7fffh 5 32 1e8000h-1effffh 4 32 1e0000h-1e7fffh 3 32 1d8000h-1dffffh 2 32 1d0000h-1d7fffh 1 32 1c8000h-1cffffh 0 32 1c0000h-1c7fffh # size (kword) address range 55 32 1b8000h-1bffffh 54 32 1b0000h-1b7fffh 53 32 1a8000h-1affffh 52 32 1a0000h-1a7fffh 51 32 198000h-19ffffh 50 32 190000h-197fffh 49 32 188000h-18ffffh 48 32 180000h-187fffh 47 32 178000h-17ffffh 46 32 170000h-177fffh 45 32 168000h-16ffffh 44 32 160000h-167fffh 43 32 158000h-15ffffh 42 32 150000h-157fffh 41 32 148000h-14ffffh 40 32 140000h-147fffh 39 32 138000h-13ffffh 38 32 130000h-137fffh 37 32 128000h-12ffffh 36 32 120000h-127fffh 35 32 118000h-11ffffh 34 32 110000h-117fffh 33 32 108000h-10ffffh 32 32 100000h-107fffh 31 32 0f8000h-0fffffh 30 32 0f0000h-0f7fffh 29 32 0e8000h-0effffh 28 32 0e0000h-0e7fffh 27 32 0d8000h-0dffffh 26 32 0d0000h-0d7fffh 25 32 0c8000h-0cffffh 24 32 0c0000h-0c7fffh 23 32 0b8000h-0bffffh 22 32 0b0000h-0b7fffh 21 32 0a8000h-0affffh 20 32 0a0000h-0a7fffh 19 32 098000h-09ffffh 18 32 090000h-097fffh 17 32 088000h-08ffffh 16 32 080000h-087fffh 15 32 078000h-07ffffh 14 32 070000h-077fffh 13 32 068000h-06ffffh 12 32 060000h-067fffh 11 32 058000h-05ffffh 10 32 050000h-057fffh 9 32 048000h-04ffffh 8 32 040000h-047fffh 7 32 038000h-03ffffh 6 32 030000h-037fffh 5 32 028000h-02ffffh 4 32 020000h-027fffh 3 32 018000h-01ffffh 2 32 010000h-017fffh 1 32 008000h-00ffffh 0 32 000000h-007fffh
47/52 m36dr432ad, m36dr432bd table 30. bank b, bottom boot block addresses m36dr432bd table 31. bank a, bottom boot block addresses m36dr432bd # size (kword) address range 55 32 1f8000h-1fffffh 54 32 1f0000h-1f7fffh 53 32 1e8000h-1effffh 52 32 1e0000h-1e7fffh 51 32 1d8000h-1dffffh 50 32 1d0000h-1d7fffh 49 32 1c8000h-1cffffh 48 32 1c0000h-1c7fffh 47 32 1b8000h-1bffffh 46 32 1b0000h-1b7fffh 45 32 1a8000h-1affffh 44 32 1a0000h-1a7fffh 43 32 198000h-19ffffh 42 32 190000h-197fffh 41 32 188000h-18ffffh 40 32 180000h-187fffh 39 32 178000h-17ffffh 38 32 170000h-177fffh 37 32 168000h-16ffffh 36 32 160000h-167fffh 35 32 158000h-15ffffh 34 32 150000h-157fffh 33 32 148000h-14ffffh 32 32 140000h-147fffh 31 32 138000h-13ffffh 30 32 130000h-137fffh 29 32 128000h-12ffffh 28 32 120000h-127fffh 27 32 118000h-11ffffh 26 32 110000h-117fffh 25 32 108000h-10ffffh 24 32 100000h-107fffh 23 32 0f8000h-0fffffh 22 32 0f0000h-0f7fffh 21 32 0e8000h-0effffh 20 32 0e0000h-0e7fffh 19 32 0d8000h-0dffffh 18 32 0d0000h-0d7fffh 17 32 0c8000h-0cffffh 16 32 0c0000h-0c7fffh 15 32 0b8000h-0bffffh 14 32 0b0000h-0b7fffh 13 32 0a8000h-0affffh 12 32 0a0000h-0a7fffh 11 32 098000h-09ffffh 10 32 090000h-097fffh 9 32 088000h-08ffffh 8 32 080000h-087fffh 7 32 078000h-07ffffh 6 32 070000h-077fffh 5 32 068000h-06ffffh 4 32 060000h-067fffh 3 32 058000h-05ffffh 2 32 050000h-057fffh 1 32 048000h-04ffffh 0 32 040000h-047fffh # size (kword) address range 14 32 038000h-03ffffh 13 32 030000h-037fffh 12 32 028000h-02ffffh 11 32 020000h-027fffh 10 32 018000h-01ffffh 9 32 010000h-017fffh 8 32 008000h-00ffffh 7 4 007000h-007fffh 6 4 006000h-006fffh 5 4 005000h-005fffh 4 4 004000h-004fffh 3 4 003000h-003fffh 2 4 002000h-002fffh 1 4 001000h-001fffh 0 4 000000h-000fffh
m36dr432ad, m36dr432bd 48/52 appendix b. common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 32, 33, 34 and 35 show the address used to retrieve each data. the query data is always presented on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure contains also a security area starting at address 81h. this area can be ac- cessed only in read mode and it is impossible to change after it has been written by st. issue a read command to return to read mode. table 32. query structure overview table 33. cfi query identification string offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 00a1h - bottom 00a0h - top device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h query unique ascii string "qry" 12h 0059h query unique ascii string "qry" 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0040h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h
49/52 m36dr432ad, m36dr432bd table 34. cfi query system interface information offset data description 1bh 0017h v ddf logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1ch 0022h v ddf logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1dh 0000h v ppf [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v ppf pin is present 1eh 00c0h v ppf [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v ppf pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0003h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0003h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0004h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0002h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
m36dr432ad, m36dr432bd 50/52 table 35. device geometry definition offset word mode data description 27h 0016h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is considered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m36dr432ad m36dr432ad erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 003eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h m36dr432ad m36dr432ad 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 003eh 32h 0000h 33h 0000h 34h 0001h
51/52 m36dr432ad, m36dr432bd revision history table 36. document revision history date version revision details 15-jan-2003 1.0 first issue. 15-jan-2003 1.1 bottom device code corrected on page 1. 25-feb-2003 2.0 document promoted from preliminary data to full datasheet status. 28-feb-2003 2.1 v ddqf signal removed from datasheet. sram input rise and fall times added to, and v ddf and v dds parameters differentiated in table 14, operating and ac measurement conditions. v dds added to the signal descriptions section.
m36dr432ad, m36dr432bd 52/52 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unite d states. www.st.com

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